MAX2871 wireless controller

SYSTEM STATUS

Detected	..	Voltage	..
Die temp.	..	Current	..
		Connection

REGISTERS

Register	Address	HEX value	DEC value
R0	000
R1	001
R2	010
R3	011
R4	100
R5	101

setup WIFI

				Website Address
				SSID
				Password

connect to hotspot

				website address	192.168.3.3/max2871
				SSID	max2871_101
				password	123456789

CONTROL MODE ..

RF OUTPUT

... MHz

FREQUENCY

FREQ. STEP

Frequency..

Lock Detect

.. MHz

START FREQUENCY

.. MHz

STOP FREQUENCY

NR. OF STEPS

TIME PER STEP

SWEEP TYPE

POWER

FREQ. RESOLUTION

OFF

INTEGER-N MODE

N (16..65535) 12500

F (0..M-1) 0

M (3..4095)4000

Freq. Res.1 kHz

DIVA 2

Fvco 2665.295 MHz

VCO nr: .. , .. Volt

Integer N mode ...

REFERENCE INPUT

Fref

MHz

R (1..1023)

doubler...

divide by 2...

Phase detector frequency (Fpfd)

MHz

PLL

Rset

kOhms

Current

Linearity

Fast Lock ..

Cycle Slip..

LD PinDigital lock

SIGMA DELTA MODULATOR

MULTIPLEXER

Rset, Current and Linearity

The MAX2871 charge-pump current is determined by the value of the resistor (Rset) from pin RSET to ground and the value of bits CP (register 2, bits 12:9) as follows: ICP = 1.63/RSET x (1+ CP<3:0>). Rset is 2.7kOhms. CP can be set between 0 and 15, resulting in charge current between 0.6 and 9.7 mA. Selecting a low current will increase lock time.
Charge pump linearity can be set between 0% and 30% and may reduce spurs. Shortest lock time is with linearity=0%. The user can determine which setting works best for their application.

Fast Lock, Fast Lock time out and Cycle Slip

Cycle Slip and Fast Lock are two methods to reduce lock time.
In Fast Lock mode the resistor Rset is temporarily reduced to a quarter of its value resulting in a higher charge pump current. In this mode CP must be set to 0. The software will take care of this. Enabling Fast Lock mode may or may not improve locktime, depending on the application. In our experience the effect is limited.
Fast-lock deactivates after a timeout set by the CDIV & FastLock Time Out button. This timeout is loop filter dependent, and is set by: tFAST-LOCK = M x CDIV/Fpfd, where M is the modulus setting and CDIV is the clock divider setting. The CDIV value can be set with the numeric display. The CDIV value will be shown in blue. The calculated FastLock Time out will be shown in red

In Cycle Slip mode lock time may or may not improve. In our experience the effect is not visible, but maybe the user has a specific application where enabling Cycle Slip is beneficial.

LD pin

The lock detect pin can output the digital lock signal, the analog lock signal (external pull up resistor of 10k required) a Low or High signal. The lock detect pin can be monitored through the LD output pin on the MAX2871 board. The LD pin is connected to a green LED. When the PLL is locked, and 'digital lock' is selected the LD output pin will be high and the LED will light up.

Sigma Delta Modulator

The sigma delta modulator controls the fractional part of the divider value (F/M). The device offers three modes for the sigma-delta modulator. Low-noise mode offers lower in-band noise at the expense of spurs. The spurs can be reduced by choosing low spur mode 1 or 2 for different modes of dithering. The user can determine which mode works best for their application.

Multiplexer

The Multiplexer is a multipurpose input/output for observing and controlling various internal functions of the MAX2871. It is available at the MUXOUT pin on the MAX2871 board.

B I T N R	V A L U E	ID	NAME	DEFINITION
31	0	INT	Int-N or Frac-N Mode Control	0 = Enables the fractional-N mode 1 = Enables the integer-N mode The LDF bit must also be set to the appropriate mode.
30		N[15:0]	Integer Division Value	Sets integer part (N-divider) of the feedback divider factor. All integer values from 16 to 65,535 are allowed for integer mode. Integer values from 0 to 15 are not allowed. Integer values from 19 to 4091 are allowed for fractional mode.
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14		FRAC[11:0]	Fractional Division Value	Sets fractional value: 000000000000 = 0 (see F0I bit description) 000000000001 = 1 ---- 111111111110 = 4094 111111111111 = 4095
13
12
11
10
9
8
7
6
5
4
3
2		ADDR[2:0]	Address Bits	Control Register address bits, 000
1
0

B I T N R	V A L U E	ID	NAME	DEFINITION
31	0	Reserved	Reserved	Reserved. Program to 0.
30		CPL[1:0]	CP Linearity	Sets CP linearity mode. 00 = Disables the CP linearity mode (integer-N mode) 01 = CP linearity 10% mode (frac-N mode) 10 = CP linearity 20% mode (frac-N mode) 11 = CP linearity 30% mode (frac-N mode)
29		CPL[1:0]	CP Linearity
28		CPT[1:0]	Charge Pump Test	Sets charge-pump test modes. 00 = Normal mode 01 = Long Reset mode 10 = Force CP into source mode 11 = Force CP into sink mode
27		CPT[1:0]	Charge Pump Test
26		P[11:0]	Phase Value	Sets phase value. See the Phase Adjustment section. 000000000000 = 0 000000000001 = 1 (recommended) ----- 111111111111 = 4095
25
24
23
22
21
20
19
18
17
16
15
14		M[11:0]	Modulus Value (M)	Fractional modulus value used to program fVCO. See the Int, Frac, Mod and R Counter Relationship section. Double buffered by register 0. 000000000000 = Not Valid 000000000001 = Not Valid 000000000010 = 2 ----- 111111111111 = 4095
13
12
11
10
9
8
7
6
5
4
3
2		ADDR[2:0]	Address Bits	Control Register address bits, 001
1
0

B I T N R	V A L U E	ID	NAME	DEFINITION
31	0	LDS	Lock-Detect Speed	Lock-detect speed adjustment. 0 = fPFD = 32MHz 1 = fPFD > 32MHz
30		SDN[1:0]	Frac-N Sigma Delta Noise Mode	Sets noise mode (see the Low-Spur Mode section.) 00 = Low-noise mode 01 = Reserved 10 = Low-spur mode 1 11 = Low-spur mode 2
29		SDN[1:0]	Frac-N Sigma Delta Noise Mode
28		MUX[2:0]	MUX Configuration	Sets MUX pin configuration (MSB bit located register 05). 0000 = Three-state output 0001 = D_VDD 0010 = D_GND 0011 = R-divider output 0100 = N-divider output/2 0101 = Analog lock detect 0110 = Digital lock detect 0111 = Sync Input 1000 : 1011 = Reserved 1100 = Read SPI registers 06 1101 : 1111= Reserved
27
26
25		DBR	Reference Doubler Mode	Sets reference doubler mode. 0 = Disable reference doubler 1 = Enable reference doubler
24		RDIV2	Reference Div2 Mode	Sets reference divide-by-2 mode. 0 = Disable reference divide-by-2 1 = Enable reference divide-by-2
23		R[9:0]	Reference Divider Mode	Sets reference divide value (R). Double buffered by register 0. 0000000000 = 0 (unused) 0000000001 = 1 ----- 1111111111 = 1023
22
21
20
19
18
17
16
15
14
13		REG4DB	Double Buffer	Sets double buffer mode. 0 = Disabled 1 = Enabled
12		CP[3:0]	Charge-Pump Current	Sets charge-pump current in mA (RSET = 5.1kohms). Double buffered by register 0. ICP = 1.63/RSET x (1+CP[3:0])
11
10
9
8		LDF	Lock-Detect Function	Sets lock-detect function. 0 = Frac-N lock detect 1 = Int-N lock detect
7		LDP	Lock-Detect Precision	Sets lock-detect precision. 0 = 10ns 1 = 6ns
6		PDP	Phase Detector Polarity	Sets phase detector polarity. 0 = Negative 1 = Positive (default)
5		SHDN	Shutdown Mode	Sets power-down mode. 0 = Normal mode 1 = Device shutdown
4		TRI	Charge Pump Output High-Impedance Mode	Sets charge-pump output high-impedance mode. 0 = Disabled 1 = Enabled
3		RST	Counter Reset	Sets counter reset mode. 0 = Normal operation 1 = R and N counters reset
2		ADDR[2:0]	Address Bits	Control Register address bits, 010
1
0

B I T N R	V A L U E	ID	NAME	DEFINITION
31	0	VCO[5:0]	VCO	Manual selection of VCO and VCO sub-band when VAS is disabled. 000000 = VCO0... 111111 = VCO63
30
29
28
27
26
25		VAS_SHDN	VAS_SHDN	Sets VAS shutdown mode. 0 = VAS enabled 1 = VAS disabled
24		VAS_TEMP	VAS_TEMP	Sets VAS response to temperature drift. 0 = VAS temperature compensation disabled 1 = VAS temperature compensation enabled
23		Reserved.	Reserved.	Reserved.
22
21
20
19
18		CSM	Cycle Slip Mode	Cycle Slip Mode 0 = Disable Cycle Slip Reduction 1 = Enable Cycle Slip Reduction
17		MUTEDEL	Mute Delay Mode	Mute Delay 0 = Do not delay LD to MTLD function to prevent flickering 1= Delay LD to MTLD function to prevent flickering
16		CDM[1:0]	Clock Divider Mode	Sets clock divider mode. 00 = Mute until Lock Delay 01 = Fast-lock enabled 10 = Phase Adjustment mode 11 = Reserved
15		CDM[1:0]	Clock Divider Mode
14		CDIV[11:0]	Clock Divider Value	Sets 12-bit clock divider value. 000000000000 = Unused 000000000001 = 1 000000000010 = 2 ----- 111111111111 = 4095
13
12
11
10
9
8
7
6
5
4
3
2		ADDR[2:0]	Address Bits	Control Register address bits, 011
1
0

B I T N R	V A L U E	ID	NAME	DEFINITION
31	0	Reserved	Reserved	Reserved. Program to 011
30
29
28		SDLDO	Shutdown VCO LDO	Sets Shutdown VCO LDO mode. 0 = Enables LDO 1 = Disables LDO
27		SDDIV	Shutdown VCO Divider	Sets Shutdown VCO Divider mode. 0 = Enables VCO Divider 1 = Disables VCO Divider
26		SDREF	Shutdown Reference Input	Sets Shutdown Reference input mode. 0 = Enables Reference Input 1 = Disables Reference Input
25		BS[9:8]	Band-Select MSBs	Sets Band-Select clock divider MSBs. See bits[19:12].
24		BS[9:8]	Band-Select MSBs	Sets Band-Select clock divider MSBs. See bits[19:12].
23		FB	VCO Feedback Mode	Sets VCO to N counter feedback mode. 0 = Divided 1 = Fundamental
22		DIVA[2:0]	RFOUT_ Output Divider Mode	Sets RFOUT_ output divider mode. Double buffered by register 0 when REG4DB = 1. 000 = Divide by 1, if 3000MHz = fRFOUTA = 6000MHz 001 = Divide by 2, if 1500MHz = fRFOUTA < 3000MHz 010 = Divide by 4, if 750MHz = fRFOUTA < 1500MHz 011 = Divide by 8, if 375MHz = fRFOUTA < 750MHz 100 = Divide by 16, if 187.5MHz = fRFOUTA < 375MHz 101 = Divide by 32, if 93.75MHz = fRFOUTA < 187.5MHz 110 = Divide by 64, if 46.875MHz = fRFOUTA < 93.75MHz 111 = Divide by 128, if 23.5MHz = fRFOUTA< 46.875MHz
21
20
19		BS[7:0]	Band Select	Sets band select clock divider value. MSB are located in bits [25:24]. 0000000000 = Reserved 0000000001 =1 0000000010 = 2 ---- 1111111111 = 1023
18
17
16
15
14
13
12
11		SDVCO	VCO Shutdown	Sets VCO Shutdown mode. 0 = Enables VCO 1 = Disables VCO
10		MTLD	RFOUT Mute until Lock Detect	Sets RFOUT Mute until Lock Detect Mode 0 = Disables RFOUT Mute until Lock Detect Mode 1 = Enables RFOUT Mute until Lock Detect Mode
9		BDIV	RFOUTB Output Path Select	Sets RFOUTB output path select. 0 = VCO divided output 1 = VCO fundamental frequency
8		RFB_EN	RFOUTB Output Mode	Sets RFOUTB output mode. 0 = Disabled 1 = Enabled
7		BPWR[1:0]	RFOUTB Output Power	Sets RFOUTB single-ended output power. See the RFOUTA+/- and RFOUTB+/- section. 00 = -4dBm 01 = -1dBm 10 = +2dBm 11 = +5dBm
6		BPWR[1:0]	RFOUTB Output Power
5		RFA_EN	RFOUTA Output Mode	Sets RFOUTA output mode. 0 = Disabled 1 = Enabled
4		APWR[1:0]	RFOUTA Output Power	Sets RFOUTA single-ended output power. See the RFOUTA+/- and RFOUTB+/- section. 00 = -4dBm 01 = -1dBm 10 = +2dBm 11 = +5dBm
3		APWR[1:0]	RFOUTA Output Power
2		C[2:0]	Register Address	Control Register address bits, 100
1
0

B I T N R	V A L U E	ID	NAME	DEFINITION
31	0	Reserved	Reserved	Reserved. Program to 0.
30		VAS_DLY	VAS_DLY	VCO Autoselect Delay. Program to 11 when VAS_TEMP=1 Program to 00 when VAS_TEMP=0
29		VAS_DLY	VAS_DLY
28		Reserved	Reserved	Reserved. Program to 000.
27
26
25		SDPLL	Shutdown PLL	Sets Shutdown PLL mode. 0 = Enables PLL 1 = Disables PLL
24		F01	F01	Sets integer mode for F = 0. 0 = If F[11:0] = 0, then fractional-N mode is set 1 = If F[11:0] = 0, then integer-N mode is auto set
23		LD[1:0]	Lock-Detect Pin Function	Sets lock-detect pin function. 00 = Low 01 = Digital lock detect 10 = Analog lock detect 11 = High
22		LD[1:0]	Lock-Detect Pin Function
21		Reserved	Reserved	Reserved. Program to 000.
20
19
18		MUX[3]	MUX MSB	Sets mode at MUX pin (see register 2 [28:26])
17		Reserved	Reserved	Reserved. Program to 00000000000.
16
15
14
13
12
11
10
9
8
7
6		ADCS	ADC Start	Sets ADC Start mode. 0 = ADC normal operation 1 = Start ADC conversion process
5		ADCM[2:0]	ADC Mode	Sets ADC mode. 000 = Disabled 001 = Temperature sensor 010 = Reserved 011 = Reserved 100 = Tune pin 101 = Reserved 110 = Reserved 111 = Reserved 2:0 ADDR[2:0] Register Address Control Register address
4
3
2		ADDR[2:0]	Register Address	Control Register address bits, 101
1
0

B I T N R	V A L U E	ID	NAME	DEFINITION
31	0	DIE[3:0]	Die ID	Die ID. 0110 = MAX2870 0111 = MAX2871
30
29
28
27		Reserved	Reserved	Reserved
26
25
24
23		POR	Power On Reset	Power-On-Reset 0 = Power has not been cycled since last read 1 = Power has not been cycled since last read. All registers have been reset to default values.
22		ADC[6:0]	ADC Code	ADC Code
21
20
19
18
17
16
15		ADCV	ADC Valid	Determines ADC code validity. 0 = Invalid ADC code 1 = Valid ADC code
14		Reserved	Reserved	Reserved
13
12
11
10
9		VASA	VAS Active	Determines if VAS is Active. 0 = VCO Autoselect complete 1 = VCO Autoselect searching for correct VCO
8		V[5:0]	Current VCO	Current VCO
7
6
5
4
3
2		ADDR[2:0]	Register Address	Control Register address bits, 110
1
0

1	Power on the MAX2871 board.
2	Connect to the MAX2871 hotspot, following the steps in the 'connect to hotspot' section.
3	Once connected to the hotspot, type in the SSID and password/network key for your WIFI network. Then press 'GET ADDRESS'.
4	After a few seconds the WIFI website address will be shown. Make a note of it.
5	Disconnect the hotspot and connect to your WIFI network. Then open the WIFI website address from step 4.
6	After a few seconds you should be connected to the Max2871 board and the web page opens. In the menubar the system status icon will show a green 'OK'.

1	Power on the MAX2871 board.
2	On your smart device or PC select the 'max2871_101' network. In some cases it might take a while before the max2871_101 is detected. In that case please refresh the network selection page.
3	Enter the network security key: 123456789
4	After a few seconds you should be connected to the hotspot. Please note that the hotspot connection is not secured and that there there is no internet access (you have a private hotspot connection). Your smart device/PC might ask you to confirm this. In that case please confirm.
5	Open your preferred web browser and open the following URL: 192.168.3.3/max2871
6	After a few seconds you should be connected to the Max2871 board and the web page opens. In the menubar the system status icon will show a green 'OK'

WIFI setup procedure

The ESP32 hotspot

Frequency

Arrow up/down

Freq. Step

Freq. Resolution

Power

Fvco, VCO nr., VCO voltage

Diva

N, F, M

lock detect graph

noise mode

integer N mode

Frequency

Arrow up/down

Freq. Step

Integer-N Mode

Power

Freq. Resolution

Fvco, VCO nr., VCO voltage

Diva

N, F, M

lock detect graph

START FREQUENCY and STOP FREQUENCY

NR. OF STEPS

TIME PER STEP

SWEEP TYPE

GO / STOP

Frequency graph

Lock Detect graph

Fref

Fpfd, R, doubler and divide by 2

Fref

Fpfd, R, doubler and 2-divide

Fref

Fpfd, R, doubler and divide by 2

Rset, Current and Linearity

Fast Lock and Cycle Slip

LD pin

Sigma Delta Modulator

Multiplexer

Rset, Current and Linearity

Fast Lock, Fast Lock time out and Cycle Slip

LD pin

Sigma Delta Modulator

Multiplexer

Rset, Current and Linearity

Fast Lock and Cycle Slip

LD pin

Sigma Delta Modulator

Multiplexer